module top(clk,
			  reset_n,
			  tft_wrx,
			  tft_rdx,
			  tft_csx,
			  tft_dcx,
			  tft_reset_n,
			  tft_d_inout,
			  tft_bl,
           SEL,
   	     DIG);



	input clk,reset_n;
	output tft_wrx,tft_dcx,tft_rdx,tft_csx;
	output  tft_bl;
	inout[15:0]tft_d_inout;
	output  tft_reset_n;
   output 		   [7:0]       SEL;
   output 		   [7:0]     	DIG;
	
	
	



	wire sys_clk_b,rst_n_b;	
	wire [15:0]	 data_t;
	wire [19:0]	 addr_t;
   wire req_t;
	wire busy;
   wire ready;
	wire	[15:0] data_b;
	wire	[19:0] addr_b;
   wire req_b;
	
	wire clk_r;
	wire [15:0]ram_rd_data;
	wire [15:0]ram_rd_addr;
	wire ram_we;
	wire [15:0]ram_wr_addr;
	wire [15:0]ram_wr_data;
	
	assign ram_we = 1'b0;
	
	

   picture_ram u2(
	               .clk(clk_r),
                  .i_we(ram_we),
                  .i_waddr(ram_wr_addr),
						.i_raddr(ram_rd_addr),
                  .i_wdata(ram_wr_data),
                  .o_rdata(ram_rd_data)
	
	);

	
	ctrl ctrl2(
	         .clk(clk),
				.reset_n(reset_n),
				.addr_t(addr_t),
				.data_t(data_t),
				.req_t(req_t),
				.busy(busy),
				.clk_r(clk_r),
				.ram_rd_data(ram_rd_data),
				.ram_rd_addr(ram_rd_addr)

				
	
	);
	
	
	
	Lcd_writer_interface  interfce1(
									//from top
										.sys_clk_t(clk),
										.rst_n_t(reset_n),
										.addr_t(addr_t),
										.data_t(data_t),
										.req_t(req_t),
									//to top
										.busy(busy),
									//from bottom
										.ready(ready),
									//to bottom
										.sys_clk_b(sys_clk_b),
										.rst_n_b(rst_n_b),
										.addr_b(addr_b),
										.data_b(data_b),
										.req_b(req_b)
);

	
 LCD_On_FPGA u22  (
						.clk(sys_clk_b),
						.reset_n(rst_n_b),
						.tft_wrx(tft_wrx),
						.tft_rdx(tft_rdx),
						.tft_csx(tft_csx),
						.tft_dcx(tft_dcx),
						.tft_reset_n(tft_reset_n),
						.tft_d_inout(tft_d_inout),
						.tft_bl(tft_bl),
                  .SEL(SEL),
   	            .DIG(DIG),
						.send_ready(ready),
						.addr_b(addr_b),
						.data_b(data_b),
						.req_b(req_b)
);





endmodule
